1. Field of the Invention
The present invention is related to semiconductor devices and manufacturing, and more particularly, to forming fin field effect transistors (FinFETs) on semiconductor wafers and methods of manufacturing Integrated Circuits (ICs) with circuits including multi-fin FinFETs.
2. Background Description
Integrated Circuit (IC) chip density and performance are primary semiconductor technology development goals. Semiconductor technology and chip manufacturing advances have improved performance through a steady increase of on-chip clock frequencies, coupled with a corresponding decrease in chip supply voltage resulting in part from reduced chip feature size.
To minimize power consumption, typical ICs are made in the well-known complementary insulated gate field effect transistor (FET) technology known as CMOS. A typical CMOS circuit includes paired complementary devices, i.e., an n-type FET (NFET) paired with a corresponding p-type FET (PFET), usually gated by the same signal. For example, a CMOS inverter is a series connected PFET and NFET pair that are connected between a power supply voltage (Vdd) and ground (GND). The pair of devices have operating characteristics that are, essentially, opposite each other. So, when one device (e.g., the NFET) is on (ideally modeled as a closed switch) and conducting current (Ion) driving a load capacitance (Cload) up or down; at the same time the other device (the PFET) is off, not conducting (ideally modeled as an open switch) and, vice versa.
Increased chip density (the average density of circuit transistors on a chip), and chip die size has increased the number of transistors packed on a single chip; while features sizes have been shrunk to pack more transistors in the same area. Another state of the art approach to increasing FET density is forming FETs vertically on narrow semiconductor surface ridges or fins. Minimum feature sized lines of semiconductor material are formed on the surface of a bulk semiconductor wafer or from the surface layer of a silicon on insulator (SOI) wafer. The semiconductor lines or ridges form fins on the surface with gates formed on the fins for tightly packed vertical FETs. These vertical FETs are known as FinFETs. Ion is directly related to the ratio of the device width to its length. Since FinFET width is limited in large part by fin height, designers form FinFET gates on multiple parallel connected fins to increase Ion in FinFET. The narrow parallel fins form non-planar source and drain regions make it challenging to contact FinFET source/drains.
One state of the art approach to contacting multi-fin FET source/drains, typically referred to as merged fin, involves epitaxially growing a highly doped semiconductor layer that merges the fins at source/drain regions. This epitaxial layer provides a uniform, planar surface for forming source/drain contacts. Another state of the art approach, typically referred to as unmerged fin, involves epitaxially growing highly doped semiconductor, e.g., diamond shaped epi, on pitched fins without the epi merging. Instead, the epi forms individual, source/drain regions at each fin.
Etching these unmerged source/drain regions, e.g., using a typical reactive ion etch (RIE), re-exposes the fins for silicide. Unfortunately, the RIE is non-selective and etches off the highly conductive epi at source/drain regions, reducing the area available for contacts. Consequently, the loss of available contact area results in higher resistance (Rs) in subsequently formed contacts. Rs is a series resistance that adds to device on impedance, and as such, reduces drive current, which reduces circuit performance. Previous approaches to minimizing the reduction in contact area have added fabrication steps, e.g., covering gates with nitride, that increased fabrication complexity and resulting fabrication costs.
Thus, there is a need for reducing FinFET contact resistance, and more particularly, a need for unmerged FinFETs with low, unmerged-fin contact resistance.